In some applications, a manufacturer or designer of electronics equipment wishes to prevent third parties from reverse engineering such equipment. The manufacturer or designer of electronics equipment often tries to prevent reverse engineering at the unit or system level, the board level, the component level or the chassis level or all of the above.
Some reverse-engineering techniques access electronics by communicating with a housed device using externally accessible interfaces. A debug or test port is typically designed to provide a mechanism by which an external device is able to inspect and change the state of various items of electronics that are internally housed in a chassis, integrated circuit housing and/or a multi-chip-module. For example, an external device can inspect and/or change the state of registers, memory or I/O interfaces of the internally housed device via a debug port or test port. Thus in some cases, a debug port or test port can be exploited to reverse engineer internally housed devices and/or chips.
The electrical systems within manufactured products often include proprietary designs. In some cases the board and/or chip manufacturers integrate the board and/or chip into systems, test the system via a test port and then sell the system to a customer. The test port or debug port is available to the customer that purchased the system.
In other cases, the board and/or chip manufacturers provide customers with a test access port that the customer uses to integrate the board and/or chip into their system. Once the customer has integrated their system, they may sell the system to yet another customer.
To facilitate the test and integration of digital integrated circuits, the Joint Test Access Group (JTAG) has developed the IEEE 1149.1 standard that defines a standard test access port and boundary-scan architecture for digital integrated circuits and for the digital portion of mixed analog/digital integrated circuits. The IEEE 1532 standard extends the IEEE 1149.1 standard to support programmable devices. Both standards provide in-system monitoring of logic states and access of boundary scan addressable memory contents. The capabilities of the JTAG interface port can be used by reverse engineers to probe the chips and boards to obtain the proprietary information about design and/or operation of the probed chips and boards.
If the information that a reverse engineer obtains by reverse engineering proprietary boards and/or chips is related to advanced military applications, the information leak may endanger national security. If the information that a reverse engineer obtains by reverse engineering proprietary boards and/or chips is related to commercial applications, the information leak could be used to undermine the economic security of the commercial vendor.
For the reasons stated above and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the specification, there is a need in the art to limit access to proprietary boards and chips via a test access port to authorized personnel.